A data network switch permits data communication among a plurality of media stations in a local area network. Data frames, or packets, are transferred between stations by means of data network switch media access control (MAC) circuitry. The network switch passes data frames received from a transmitting station to a destination station based on the header information in the received data frame.
Packet transmission events typically are tracked provide a basis for statistical analysis of network operation with respect to each data network switch port. For example, the number of transmitted packets, received packets, transmission collisions and the like can be counted and polled periodically. These significant parameters, termed objects, may be collected for purposes of statistical analysis. Through the use of counters, determination can be made of improper device operation such as, for example, loss of packets.
Typically, each MAC unit may include a receive state machine and a transmit state machine having internal counters of limited capacity for counting a small number of transmission event parameters for each frame that traverses the respective switch port. Flip-flops, dedicated to the particular parameter objects, are respectively incremented each time an item in that frame is identified. For each incoming frame, which may be temporarily stored in a receive FIFO buffer, the respective flip-flops in the receive state machine are read and the resulting data are appended to the frame. For outgoing frames, similar processing takes place. This data traditionally has been stored on the chip in history or status registers.
As data networks become more robust and data traffic increases, additional operational parameters become significant. For example, ports may be operative with different transmission characteristics, such as different data rates and at half-duplex or full-duplex protocols. The need to track all significant parameters imposes difficulties relating to increased MAC complexity. Such complexity involves the provision of more registers and supporting logic elements, as well as a requirement for larger buffer capacities. Integration of these additional elements for each MAC on the switch logic chip places a burden on chip architecture. These projected difficulties, and the relatively limited reporting functionality for the prior art arrangements, are significant disadvantages.
More recent network switch arrangements include a RAM based memory on the switch logic chip as a full counter for data received from all of the MACs on the chip. Incorporation of a large capacity RAM in the chip to accommodate operational parameter data from all ports incurs undesirable expense. As the number of parameters increases to keep up with expanding statistical requirements, available RAM capacity must meet these needs. Polling of the RAM for external statistical diagnostic functions would require transfer of significantly increased quantities of data. Space constraints inherent in the integration of the various elements on a single logic chip impose additional drawbacks.
The accumulation of this increased operational parameter data and the frequent access thereof for statistical processing imposes additional operational considerations. Traffic events and parameters of interest are monitored as they occur and contemporaneously added during the course of operation. The data may be retrieved frequently to perform appropriate statistical processing to analyze normal operation or for diagnostic purposes during a testing period.
The aforementioned commonly assigned related applications (Our Docket Nos. 1033-241 and 1033-242) recognize the demands on chip architecture engendered by increased MAC complexity, increased number of switch ports and usage, and increased number of significant operational parameters. These applications address the chip architecture demands by defining significant event parameters as objects of a Management Information Base (MIB). An Integrated Multiport Switch (IMS) includes all logic components on a single chip. The network switch architecture includes an on-chip "MIB engine" having a MIB report processor that enables monitoring of a large number of MIB objects by each on-chip MAC, ultimately to be stored in external memory, while minimizing MAC complexity. A MAC for each port in the switch output a MIB report for each transmission or reception of data according to a specific encoded format to the MIB engine. The MIB engine decodes the MIB report into a plurality of associated MIB objects, which are temporarily accumulated until the external memory is updated. The MIB engine initiates the stored MIB value updating process by retrieving the values from the external memory and adding the accumulated MIB objects to the retrieved values. The updated MIB objects are then transmitted back to the external memory for storage therein and the MIB engine object values are reset.
The MIB engine described in the aforementioned applications receives MIB reports from each MAC port on a time-shared basis. While time slots of a recurring sequence of clock cycles for reception of MIB report data by the MIB engine may be nominally assigned to respective ports, the flow of data traffic at the plurality of ports is of a random, rather than steady state, nature. Ports may operate variously according to half-duplex or full duplex protocols and at different transmission rates. Ports may be idle for substantial periods of time, while at other times the switch bears traffic conditions up to full capacity. When data communication occurs concurrently for a plurality of ports, loss of MIB report data must be avoided. MIB report transmission to the MIB engine in accordance with switch port characteristics should be prioritized.